Focus: The TakeCharge Design Kit is a total ESD design and layout solutions package, either pre-developed independently by Sarnoff Europe for selected foundry processes and a generic application set, or custom developed under a project for a proprietary process and a custom application set. The TakeCharge Design Kit is ready for dissemination to your engineers.

Value add: The TakeCharge Design Kit provides your engineers with silicon proven solutions and integration tools for direct application and first-time-right ESD design in product IC's.

Key deliverables: The key deliverables of a TakeCharge Design Kit include:

• ESD design and layout: strategy and solutions
• Fully integrated calculation tool, based on silicon proven scaleable models and parameters - ESD design: performance and dimensions; device to SOC - Normal operation design: capacitance, leakage, area...
• Decision tree for easy selection of optimal design choices
• Golden reference designs, including: - Reference layout (GDSII) - Geometry scaling and IC/IO implementation guidelines
• 2 day training
• Product implementation support through the Basic Support Package
• All deliverables are professionaly documented along two main dividers: -Generic versus Technology Specific information - Design versus Layout information

Business model:

• The TakeCharge Design Kit for standard CMOS foundry processes is delivered in an attractive leveraged model.
• The TakeCharge Design Kit for proprietary processes is a fixed fee custom project with milestone payment scheme based on agreed schedule and deliverables.

The commercial use of the TakeCharge Design Kit deliverables requires execution of a TakeCharge IP License Agreement.