foundry partners
Papers
Published Papers
Overview papers- Outlook on ESD protection approaches
- ESD for sub-90nm CMOS technologies
- SCR's in SOI
- ESD solutions for High Voltage technology [1] / [2]
- ESD protection for advanced nodes
- TakeCharge ®
ESD Analysis papers
- VFTLP analysis [1] / [2]
- MM - HBM correlation issues
Protection devices
- SCR solutions
- Transient Device Behavior of SCRs
- RTSCR
- High Holding Current SCR
- DTSCR
- Silicon Controlled Rectifier (SCR)
- MOS solutions
- Bulk coupling in SOI NMOS
- Active-Area-Segmentation (AAS)
- Multi-Finger Turn-on (MFT)
- Back-End Ballast (BEB)
- Other
- Active Source Pump
Transient Device Behavior of SCRs
Paper presented at the EOS/ESD symposium (September 2007)
To download, please login or register for free here.Abstract - New insights regarding the interpretation of the VFTLP IV-curve and the fast transient current and voltage waveform data are presented. These insights are used to determine the design factors affecting the turn-on time and triggering behavior of SCRs in a 90 nm bulk CMOS technology
Paper presented at ESDA IEW conference at Stanford Sierra Conference Center in South Lake Tahoe, California (May 14-17, 2007)
To download, please login or register for free here.Abstract - The Transmission Line Pulse (TLP) test system has long been used as an analysis tool to complement the pass:fail HBM and MM qualification data. Recently a new TLP system (Very Fast TLP - VFTLP) has become available, which uses much shorter pulse durations (1-10 ns) and much faster rise times (100-200 ps) than the conventional TLP system (typically 100 ns and 10ns respectively). This VFTLP system opens up new possibilities for studying the ESD protection device behavior in the nanosecond time domain, including characterization of turn-on time and voltage overshoot. This work provides an overview of the interpretation of the VFTLP measurement data.
Poster presented at ESDA IEW conference at Stanford Sierra Conference Center in South Lake Tahoe, California (May 14-17, 2007)
To download, please login or register for free here.Abstract - HBM and MM are important standards for ESD testing and typically correlate well. In some notable cases however, MM shows much lower failure levels than HBM. One of the most important physical mechanisms responsible for this is dynamic avalanching. This paper provides an example of such a dynamic avalanching failure, and includes a description of the physics involved.
Paper presented at the RCJ symposium in Tokyo, Japan (November 30 - December 1, 2006)
To download, please login or register for free here.Abstract - The Transmission Line Pulse (TLP) test system has long been used as an analysis tool to complement the pass/fail HBM and MM qualification data. Recently a new TLP system (Very Fast TLP - VFTLP) has become available, which uses much shorter pulse durations (1-10 ns) and much faster rise times (100-200 ps) than the conventional TLP system (typically 100 ns and 10 ns respectively). This VFTLP system opens up new possibilities for studying the ESD protection device behavior in the nanosecond time domain, including characterization of turn-on time and voltage overshoot. However, the analysis of the results obtained by a VFTLP requires a deeper understanding. This paper provides an overview of the possibilities, the pitfalls and the constraints, as well as new insights regarding the interpretation of the VFTLP measurement data.
Paper presented at the EOS/ESD symposium (September 2006)
To download, please login or register for free here.Abstract - Multi-finger SOI MOS devices exhibit a low ESD failure current, related to the thin Si-film and the complete isolation of the transistor body regions, causing non-uniform conduction in bipolar snapback mode. The traditional layout approaches (silicide blocked junctions, increased gate length) are compared and a novel layout concept is proposed to improve uniform triggering. Excellent ESD performance around 3mA/um2 is achieved for minimum dimension, fully silicided devices in a 90nm SOI technology.
ESD solutions for High Voltage technology
Paper published at Microelectronics Reliability (December 2005)
To download, please login or register for free here.Abstract - There is a trend to revise mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation problems and the creation of unexpected weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.
Outlook on ESD protection approaches
Paper presented at Taiwan ESD symposium (November 2005)
To download, please login or register for free here.
Abstract - Due to the continuous scaling of the CMOS technology, ESD protection design is ever more challenging. Thinner gate oxides and sensitive output drivers drastically reduce the available voltage margin for the traditional protection approaches.
Moreover, new applications with RF and high speed interfaces further reduce the available options. Stringent CDM requirements create new failure modes in the core of the System-On-Chip (SOC) IC's. This paper presents an overview of the current protection approaches and their applicability for the emerging IC's and systems in advanced technology nodes.
ESD for sub-90nm CMOS technologies
Paper presented at ISCAS International Symposium on Circuits and systems Kobe Japan (May 22nd-26th, 2005)RTSCR
To download, please login or register for free here.Abstract - This paper presents a protection strategy for ultra-sensitive IO's containing thin gate oxides, while combining two complimentary ESD design approaches:
- Low-voltage diode-chain triggering SCR clamps that allow for efficient voltage clamping.
- Active-Source-Pump circuits applied for effective expansion of narrow ESD design windows for ultra-thin GOX protection. This focus of the paper is on the ASP schemes while some RF aspects will be covered as well.
Paper presented at ESD/EOS Symposium Anaheim, CA (September 11th-16th, 2005)
To download, please login or register for free here.
Abstract - a local protection scheme for output drivers is presented, solving the competitive triggering issue using only a very small series (~10 Ohm) resistance. This novel solution uses an SCR that is triggered by current flowing through the driver in ESD mode.
Paper presented at ESD/EOS Symposium Anaheim, CA (September 11th-16th, 2005)
To download, please login or register for free here.
Abstract - This paper introduces an SCR based ESD protection design for SOI technologies. It is explained how efficient SCR devices can be constructed in SOI. These devices outperform MOS devices by about 4 times. Experimental data from 65nm and 130nm SOI is presented to support this.
ESD protection for advanced nodes
Paper presented at CICC Custom Integrated Circuits Conference San Jose CA (September 18th-21st, 2005)
To download, please login or register for free here.
Abstract - This paper reviews the application of SCR-based ESD protection circuits in advanced CMOS/SOI technologies. The devices are integrated in a flexible modular circuit design technique allowing for independent optimization of key characteristics. The IC application focus is on sensitive IOs, i.e. (ultra-)thin GOX input protection and robust output driver design using SCRs. Moreover, SCR transfer and integration into advanced SOI technologies is discussed. RF ESD principles are considered as well.
Paper presented at IEEE Custom Integrated Circuits Conference in Orlando, FL (October 3-6, 2004)
To download, please login or register for free here.
Abstract - This paper presents a novel active-source-pump (ASP) circuit technique to significantly lower the ESD sensitivity of ultra thin gate inputs in advanced sub-90nm CMOS technologies. As demonstrated by detailed experimental analysis, an ESD design window expansion of more than 100% can be achieved. This revives conventional ESD solutions for ultra sensitive input protection also enabling low-capacitance RF protection schemes with a high ESD design flexibility on IClevel. ASP IC application examples and the impact of ASP on normal RF operation performance are discussed.
Paper presented at 26th EOS/ESD Symposium in Grapevine (Dallas), TX (September 19-23, 2004)
To download, please login or register for free here.
Abstract - There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.
paper presented at 2003 IEEE International Electron Device Meeting, December 8-10, 2003, Hilton Washington and Towers, Washington DC, USA.
To download, please login or register for free here.
Abstract - A novel Diode-Triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application in very narrow ESD design windows. Trigger voltage engineering in conjunction with efficient SCR voltage clamping enables the protection of ultra-sensitive circuit nodes, such as SiGe HBT bases (e.g. LNA input in BiCMOS-0.35u) and thin gate-oxides (e.g. tox=1.7nm in CMOS-0.09u). SCR integration is possible based on CMOS-layers or high-speed SiGe HBT’s.
Active-Area-Segmentation (AAS)
Paper presented at 25th EOS/ESD Symposium in Las Vegas, NV (September 21-25, 2003)
To download, please login or register for free here.
Abstract - This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13um and a 0.18um CMOS technology obtaining HBM ESD capability of up to 8.6V/um2.
Paper presented at 24th EOS/ESD Symposium in Charlotte, NC (October 6-10, 2002)
To download, please login or register for free here.
Abstract - this paper presents a novel SCR for power line and local IO ESD protection. The HHI-SCR exhibits a dual ESD-clamp characteristic: low-current high-voltage clamping and high-voltage low-current clamping. These operation modes enable latch-up immune operation...
To download, please login or register for free here.
Abstract - this paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and ESD protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um² HBM were demonstrated...
Silicon Controlled Rectifier (SCR)
Paper presented at 23rd EOS/ESD Symposium in Portland, Oregon (September, 2001)
To download, please login or register for free here.
Abstract - in this paper, design aspects, operation, protection capability and applications of SCRs in deep sub-micron CMOS processes are addressed. A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR. Experimental verification, including endurance testing, demonstrates...
Award Best paper presentation award EOS/ESD Symposium 2001
Presented by Markus Mergens on the 23rd EOS/ESD Symposium in Portland Oregon (September 2001)
To download, please login or register for free here.
Abstract - A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations...
Paper presented at 22nd EOS/ESD Symposium in Anaheim, CA (September 26-28, 2000)
To download, please login or register for free here.
Abstract - A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced [1]. This novel design solution can be implemented straightforwardly without process modifications. ESD performance levels obtained in different 0.25um and 0.18um CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economic silicon real estate consumption...