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Overview of available patents
Sarnoff Europe owns a very significant portfolio of on-chip ESD protection patents. This portfolio does not only cover patents on device level, but also includes circuit level, and full IC level patents. Below is an overview list of Sarnoff Europe’s ESD protection patent portfolio including the US patent number. These patents are also registered in other countries.
ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES HAVING HIGH HOLDING CURRENT FOR LATCH-UP IMMUNITY
Abstract: An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE WITH SIMULTANEOUS AND DISTRIBUTED SELF-BIASING FOR MULTI-FINGER TURN-ON
Abstract: An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/0 pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being couvled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/0 pad of the IC and the first gate ofthe NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.
MINIMUM-DIMENSION, FULLY-SILICIDED MOS DRIVER AND ESD PROTECTION DESIGN FOR OPTIMIZED INTER-FINGER COUPLING
Abstract: An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I10 periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate
region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.
LOW VOLTAGE SILICON CONTROLLED RECTIFIER (SCR) FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION OF SILICON-ON-INSULATOR TECHNOLOGIES
Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SO1 protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device
METHOD AND APPARATUS FOR PROTECTING A GATE OXIDE USING SOURCE/BULK PUMPING
Abstract: A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.
METHOD AND APPARATUS FOR PROVIDING CURRENT CONTROLLED ELECTROSTATIC DISCHARGE PROTECTION
Abstract: It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below.
SILICON CONTROLLED RECTIFIER ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR POWER SUPPLY LINES WITH POWERDOWN MODE OF OPERATION
Abstract: An electrostatic discharge (ESD) protection device, for protecting power lines of an integrated circuit. In one embodiment, the ESD protection device includes a first silicon controlled rectifier (SCR) coupled between a first power line and a second power line, and a second SCR coupled anti-parallel to the first SCR between the first and second power lines. A first trigger device is coupled to the first power line and a first trigger gate of the first SCR, and a second trigger device coupled to the second power line and a first trigger gate of the second SCR. The trigger devices and the SCRs provide power-down-mode-compatible operation of the power lines, as well as ESD protection.
ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES HAVING HIGH HOLDING CURRENT FOR LATCH-UP IMMUNITY
Abstract: An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.
SILICON CONTROLLED RECTIFIER ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH EXTERNAL ON-CHIP TRIGGERING AND COMPACT INTERNAL DIMENSIONS FOR FAST TRIGGERING
Abstract: A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.
ELECTROSTATIC DISCHARGE PROTECTION SILICON CONTROLLED RECTIFIER (ESD-SCR) FOR SILICON GERMANIUM TECHNOLOGIES
Abstract: An electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for protecting circuitry of an integrated circuit (IC). The SCR includes a N-doped layer disposed over a substrate and a first P doped region disposed over the N-doped layer. At least one first N+ doped region forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N+ doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.
ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES FOR HIGH SPEED TECHNOLOGIES WITH MIXED AND ULTRA-LOW VOLTAGE SUPPLIES
Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit includes a pad, adapted for connection to a protected circuit node of the IC, and an ESD protection device, which is coupled between the pad and ground. A diode turn-on device is coupled in a forward conduction direction from the pad to a first gate of the ESD protection device. In a second embodiment, the ESD protection circuit is an SCR having an anode coupled to a first voltage supply line, and a cathode coupled to ground. A parasitic capacitance is coupled between each the voltage supply line and the grounded cathode.
MULTIFINGER SILICON CONTROLLED RECTIFIER STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION
Abstract: An electrostatic discharge (ESD) protection circuit including a silicon controlled rectifier having a plurality of SCR fingers. Each SCR finger includes at least one interspersed high-doped first region formed within a first lightly doped region. At least one interspersed high-doped second region are formed within a second lightly doped region, where the first and second lightly doped regions are adjacent one another. At least one first trigger-tap is coupled to the second lightly doped region. Additionally, at least one first low-ohmic connection is respectively coupled between the at least one first trigger tap of each SCR finger.
DOUBLE TRIGGERING MECHANISM FOR ACHIEVING FASTER TURN-ON
Abstract: An ESD protection circuit includes a SCR and a switching means, such as a MOS transistor connected to the SCR so that the SCR is turned on by the switching means to allow an ESD pulse to pass from a Pad line to a grounded VSS line and thereby dissipate the ESD pulse. The SCR is connected between the Pad line and the VSS line. One MOS switching means is connected between the Pad line and the SCR and has a gate which is connected to a Vdd line which maintains the switch in open condition during normal Vdd bias conditions. An ESD pulse applied to the Pad line, the switch is preconditioned in ON mode allowing the SCR to be predisposed to conduction to allow the ESD pulse to flow to the VSS line.
STACKED SILICON CONTROLLED RECTIFIERS FOR ESD PROTECTION
Abstract: An exemplary embodiment of the invention eliminates the common P-Well in a stacked SCR structure by providing isolated P-Wells. This embodiment is particularly advantageous in electrostatic protection devices (ESD) formed from a plurality of silicon controlled rectifiers connected in series. The isolated P- Wells are formed, in part, by a high voltage CMOS process incorporating a relatively heavily doped retrograde buried N layer that enables the formation of junction isolated P-Wells surrounded by an N-Well. The complete isolation of the P- Well prevents the normal P- Well to P substrate short, enabling more effective triggering of stacked SCRs. Advantages of implementing isolated P-Wells over a common P-Well in a stacked SCR electrostatic protection device, include faster triggering, lower current triggering, and a reduction in the number of triggering structures required. These advantages are desirable for deep sub-micron ESD protection structures.
APPARATUS FOR CURRENT BALLASTING ESD SENSITIVE DEVICES
Abstract: A current ballasting circuit for an ESD protection device couples nonintersecting conductive strips between a common contact pad and the contact electrodes of the ESD protection device. The connecting strips form respective electrically isolated ballasting resistors between the external contact pad and the contact electrodes of the ESD device. In addition, lateral resistances are formed between the contact strips which enhance the operation of the multiple ballasting resistors. The conductive strips may be made from metal, polysilicon or by a vertically meandering series connection of polysilicon layers, metal layers and interconnecting vias. The lateral resistance between the parallel conductive paths may be enhanced by segmenting both the drain and source electrodes. In one example, the gate electrode of an MOS ESD device extends locally between each pair of strips to segment the drain and source regions. The lateral resistance between the conductive strips is further enhanced by defining an additional gate electrode, having a portion that is parallel to the gate electrode of the ESD device and further portions that extend between the conductive strips. Multiple ESD devices may be connected in parallel to provide additional paths for shunting ESD current.
MULTI-FINGER CURRENT BALLASTING ESD PROTECTION CIRCUIT AND INTERLEAVED BALLASTING FOR ESD-SENSITIVE CIRCUITS
Abstract: A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate terminals of at least one of the at least two FETs are configured to be biased by an ESD potential applied to the drain electrodes to reduce the turn-on potential of the ESD device. At least two second resistive channels are connected between a corresponding one of the source terminals of the at least two FETs and a circuit return path.
ADJUSTABLE TRIGGER VOLTAGE CIRCUIT FOR SUB-MICROMETER SILICON IC ESD PROTECTION
Abstract: An electrostatic protection (ESD) circuit for an integrated circuit (IC) includes a string of a plurality of diodes connected between a Vss line and a Vdd line. A first PMOS transistor and a first NMOS transistor are connected in series between the Vdd line and the string of diodes. The first PMOS transistor has a gate connected between two of the diodes of the string, and the NMOS transistor has a gate connected to the Vdd line. A second PMOS transistor and a second NMOS transistor are connected in series between the Vss line and the Vdd line with the PMOS transistor having a gate connected to the junction between the first PMOS transistor and the first NMOS transistor and the second NMOS transistor having a gate connected to the Vdd line. A clamp NMOS transistor is connected between the Vss line and the Vdd line and has a gate connected to the junction between the second PMOS transistor and the second NMOS transistor. A diode may be connected between the Vdd line and the second PMOS transistor
CIRCUITS FOR DYNAMIC TURN OFF OF NMOS OUTPUT DRIVERS DURING EOS/ESD STRESS
Abstract: A circuit for the protection of an output driver NMOS transistor during EOS/ESD stress includes an output driver NMOS transistor and an output driver PMOS transistor connected in series between a Vss line and a Vdd line with the gates of the output driver transistors being connected together. An I/O pad is connected to the junction of the output driver transistors. A pre-driver NMOS transistor and a pre-driver PMOS transistor are connected in series between the Vss line and the Vdd line with the gates of the out-put driver transistors being connected together with the output of the pre-driver transistors being connected to the gates of the output driver transistors. A gate clamp is connected between the Vss line, the I/O pad the junction between the pre-driver transistors and the gate of the output driver NMOS transistor. An ESD clamp is connected between the I/O pad, the Vss line and the gate clamp. The gate clamp may comprise a trigger circuit and an inverter circuit with the trigger circuit being either a capacitor and a resistor, or a resistor, MOS transistor and a Zener diode. The circuit may include a plurality of stages of pre-driver transistors.
Crisscross voltage level shifter
Abstract: A crisscross level shifter comprising a pull-down circuit configured as a pair of cascode amplifiers and a crisscross pull-up circuit. The cascode amplifiers are enhanced by a feedforward circuit coupling, for both amplifiers, the input of one cascode amplifier to the output of the other cascode amplifier.
ELECTROSTATIC PROTECTION STRUCTURE FOR MOS CIRCUITS
Abstract: An ESD protection circuit includes a pair of NPN lateral transistors electrically connected in series with the emitter of one of the transistors. The bases of the two transistors are electrically connected together and are floating. The two transistors may be provided by two MOS transistors having N-type source and drains and P-type channel regions. The channels regions are connected together and are floating.
Electrostatic protection circuit
Abstract: An ESD protection circuit includes a portion for protecting a pair of power lines and a portion for protecting an input/output pin. The power line protection portion includes at least three SCRs electrically connected in series between the power lines. A zener diode is electrically connected between a gate of the SCR at one end of the series and the negative power line, and a resistor is electrically connected between the gate of the one SCR and the positive power line. The gates of the other SCRs in the series are electrically connected to the negative power line or to their own cathode. The I/O pin protection portion includes a plurality of SCRs connected in series between the power lines with the I/O pin being connected between the SCR at one end of the series and the next adjacent SCR in the series. A separate zener diode is electrically connected between the gate of the SCR at the one end of the series and the gate of the next adjacent SCR and the negative power line. A separate resistor is connected between the gate of the SCR at the one end of the series and the next adjacent SCR and the positive power line. The gates of the other SCRs in the series are connected to the negative power line or to their own cathode.
ESD PROTECTION CIRCUIT FOR INTEGRATED CIRCUIT
Abstract: An ESD protection circuit includes a portion for protecting a pair of power lines and a portion for protecting an I/O pin. The power line protection portion includes at least three SCRs electrically connected in series between the power lines. A zener diode is electrically connected between a gate of the SCR at one end of the series and the negative power line, and a resistor is electrically connected between the gate of the one SCR and the positive power line. The gates of the other SCRs in the series are electrically connected to the negative power line or to their own cathode. The I/O pin protection portion includes a plurality of SCRs connected in series between the power lines with the I/O pin being connected between the SCR at one end of the series and the next adjacent SCR in the series. A separate zener diode is electrically connected between the gate of the SCR at the one end of the series and the gate of the next adjacent SCR and the negative power line. A separate resistor is connected between the gate of the SCR at the one end of the series and the next adjacent SCR and the positive power line. The gates of the other SCRs in the series are connected to the negative power line or to their own cathode.
ELECTROSTATIC DISCHARGE PROTECTION FOR AN ARRAY OF MACRO CELLS
Abstract: An electrostatic discharge (ESD) protection circuit for an integrated circuit formed of a plurality of individual circuit cells which are connected to form the desired circuit. A pair of buss lines, preferably in closely spaced relation, extend about the circuit formed by the circuit cells. A plurality of ESD protection circuits are electrically connected between the buss lines in a spaced apart relationship, preferably in a close relationship to the electrical connections of the circuit cells to be protected.
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR A NMOS OR LATERAL NPN TRANSISTOR
Abstract: An electrical circuit including an NMOS or lateral NPN bipolar transistor includes a zener diode connected thereto to provide ESD protection for the transistor. The NMOS transistor includes an N-type source, an N-type drain, a P-type channel region and a gate over and insulated from the channel region. The zener diode is electrically connected between the gate and the drain of the NMOS transistor with the anode of the zener diode being connected to the gate and the cathode of the zener diode being connected to the drain. For some purposes the anode of the zener diode is positioned close to the gate to provide the desired ESD protection. The lateral NPN bipolar transistor includes an N-type emitter and collector and a P-type base. The zener diode is connected between the collector and the base with the anode of the zener diode being connected to the base and the cathode of the zener diode being connected to the emitter.
SCR ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUITS
Abstract: The invention is a protection circuit for an integrated circuit which includes an SCR switch, a zener diode in parallel with the SCR to trigger the SCR to its on-state, and a zener diode in series with the SCR controls the on-state or clamping voltage of the SCR. The protection circuit is formed in a semiconductor substrate of first conductivity type having a well region of second conductivity type, a first region of first conductivity type in the well and a second region of second conductivity type in the substrate spaced from the well region. The first region, well region, substrate and second region forming the SCR. A third region of second conductivity type is in the well region and contacts the first region to form a first zener diode. A fourth region of second conductivity type is in the substrate and electrically connected to the well region. A fifth region is in the substrate and contacts the fourth region to form a second zener diode
SCR protection structure and circuit with reduced trigger voltage
Abstract: A low breakdown voltage device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage compatible with submicron integrated circuit fabrication processes. A low breakdown voltage SCR protection circuit is also disclosed.
LOW TRIGGER VOLTAGE SCR PROTECTION DEVICE AND STRUCTURE
Abstract: A device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage.
Low voltage triggered snap-back device
Abstract: A protection device for an integrated circuit includes short and longer channel length structures, each of which provides a parasitic bipolar transistor, connected between a terminal of the integrated circuit and a source of reference voltage. The short channel length structure has a breakdown voltage greater than the supply voltage for the integrated circuit, and less than the insulator damage threshold of the integrated circuit. The conduction through the short channel length structure after initiation of a transient phenomena causes the longer channel length structure to conduct before the transient exceeds the breakdown voltage of the integrated circuit and the short channel length structure. The longer channel length structure operates in the "snap-back" conduction mode when the current density exceeds a critical value to conduct away the transient energy.