Background

Recently, advanced SOI technology nodes are being used more extensively due to a number of advantages mainly related to the reduction of power consumption, smaller silicon area, lower gate delay and reduced parasitic junction capacitance. Moreover, due to the completely isolated transistors, latch-up is no longer an issue. However SOI technology comes also with disadvantages such as the higher cost for the starting material, floating body and history effects, increased self-heating issues and a higher design complexity.

ESD complexity

Due to the thin silicon film and insulating properties of the buried oxide, ESD devices in SOI are expected to have a significantly lower performance than devices in a Bulk process. For the same reason, the SOI devices also have a significantly higher on resistance. This implies a severe penalty on the consumed silicon area and capacitance due to larger ESD structures. For NMOS/PMOS transistors, the complete isolation in SOI (BOX and STI) also limits the transfer of the base potential between adjacent fingers further reducing the applicability of publicly available solutions.

Experience from Sarnoff

Sarnoff has developed ESD solutions for a number of SOI technologies:

Application	CMOS node
High performance computing applications	90nm (PD) – 65nm (PD)
Computing platform feasibility study	90nm (BST)
General and high temperature applications	130nm (PD)

PD = Partially Depleted SOI
BST = Body Slightly Tied SOI

Key technical benefits for working with Sarnoff

IC designers have worked with Sarnoff to receive optimized ESD solutions for SOI technologies.
For SOI, Sarnoff has focused on different items:

• Area efficient ESD solutions through the use of optimal diode, NMOS and SCR layouts.
• Low capacitive, low resistive
  • High ESD protection with low cap
  • Low-to-zero resistance in the pad
• Scalable ESD performance to allow any ESD requirement on-chip.
• Low leakage
• Over voltage tolerant options available

Example circuit protection

Sarnoff has focused on a number of aspects to improve ESD protection capabilities in SOI technologies. Some examples are provided below.

• The use of optimized diode layout can re-enable dual diode based protection strategies.
  
• Due to the thin SOI film and isolated body regions in multi finger devices, the NMOS snapback performance is typically about 4 times lower as compared to similar sized NMOS devices in bulk technology. Sarnoff has developed special layout techniques to improve NMOS snapback behavior without the need for silicide blocked drain junctions.
  
• ESD devices such as the NMOS transistors have limited clamping efficiency in SOI technologies. Sarnoff has developed a patented layout to create Silicon Controlled Rectifiers in SOI technology with a much improved clamping behavior
  

Customer testimonial

• Renesas Technology
  • Renesas Technology has signed a license agreement with Sarnoff Europe covering TakeCharge® ESD protection circuitry for Renesas Technology's SOI products, including 90nm and 65nm devices. By utilizing TakeCharge®, Renesas Technology plans to supply the marketplace with optimized and compact SOI products offering strong ESD protection while reducing the amount of time required for design and development
  • TakeCharge® ESD provides a high level of ESD protection in a smaller surface area, which allows the development of smaller chips. Finally, it has low parasitic capacitance, making it ideal for use in high-speed applications.   [read more]

Relevant conference publications

Sarnoff engineers frequently publish technical peer-reviewed papers about the ESD solutions. A selection of these publications regarding SOI technology is provided below

• Concept for Body Coupling in SOI MOS Transistors to Improve Multi-Finger Triggering – EOS/ESD symposium (2006)
• SCR based ESD protection in nanometer SOI technologies – EOS/ESD symposium (2006)
• Advanced ESD Protection Circuits in CMOS / SOI Nanotechnologies – CICC (2005)