Background

Today, IC makers turn to the most advanced technology nodes like 65nm and 45nm for applications that require high performance computing power. The most obvious applications are the microprocessors CPU’s for desktop, server and super computers. However, also the graphical processors can benefit from the most advanced technology nodes. Similarly, the upcoming high definition multi media players such as HD-DVD or Blu-ray recorders require strong encoding schemes (H.264) to maximize the recording time on a disc. These applications all need raw processing power, only to be found in the advanced technology nodes where integration of >200 million transistors is feasible.
However, the consumer electronics applications are growing into advanced nodes too, where high production volume, small die area, System-on-Chip integration and low power are the drivers. Certainly for these applications, the fabrication plant must ensure fast volume ramp up, high reliability and yield. Moreover, much more than for past technology nodes, the fabs/foundries must provide different process flavors, many Vth versions and process options for RF and memory to fulfill all the different needs. The main differentiators are speed/performance, cost, power/leakage and SoC integration.

ESD complexity

Advanced CMOS nodes bring a number of problems for the ESD designers. In advanced CMOS, the core transistors are extremely sensitive to ESD. Efficient core protection must be in place. At 65nm and 45nm, the (1.0 – 1.2V) core transistors are damaged when the voltage rises above 3-4V, even for a short time.
 
For the high performance computing applications, the communication bandwidth should not be limited by parasitic capacitance from the ESD solutions, even when IO designers turn to complex interfaces build up using the sensitive core devices for maximum speed.
Similarly, low power ESD solutions are a must-have for any consumer electronics application. But above all, the ESD solutions must be flexible to cover all the different process flavors and transistor variations the technology people have created. Perhaps the most important complexity is the rising mask cost (>$3Million) for 45nm, leaving no room for failure.

Experience from Sarnoff

Through a close cooperation with its partners (IDM, foundry and fabless), Sarnoff has access to the most advanced process technology, including 45nm, well ahead of the introduction of first products. This ensures Sarnoff can provide solutions to the fast-paced market in a timely fashion. Sarnoff has focused on the development of highly efficient power protection cells, low capacitive solutions and foremost, flexible and portable clamp devices.
 

Currently the following IC applications including TakeCharge ESD solutions are available on the market in 65nm technology: High performance FPGA’s, High performance computing ASIC’s, gaming and graphics processing units. Sarnoff has strong ties to two foundries offering state-of-the-art 65nm technology including Sarnoff ESD solutions to the fabless customers worldwide.

Key technical benefits for working with Sarnoff

IC designers have worked with Sarnoff to receive robust ESD solutions for advanced IC applications without compromising product performance.
For advanced CMOS technologies, Sarnoff has focused on different items:

• Effective protection of thin oxide devices, even when directly connected to the pad
• Area efficient ESD solutions to reduce the total ESD area as much as possible.
• Low capacitive, low resistive
• High ESD protection with low cap: 100fF-200fF for 4kV
• Low-to-zero resistance in the pad
• Scalable ESD performance to allow any ESD requirement on-chip.
• Low leakage and Latch-up immune devices
• Over voltage tolerant options available
• Solutions are pre developed and proven in more than 5 proprietary 65nm technology flavors. Concepts are proven down to 45nm.

Example circuit protection

An example of a protection concept for a 65nm GOX1 (1.0V) input application is depicted below. The end user required 200V Machine Model (MM) on-chip ESD protection.

Low leakage during normal operation: 1nA @ 1.2V Low capacitive full local protection of sensitive analog IO: Total junction capacitance <140fF Small area for local protection: 1200 um2 Low noise, high speed enabled: No series resistance inserted between pad and input/analog IO Effective protection: full local clamping

Customer testimonials

• Naoyuki Shigyo, Chief Specialist, System LSI Design Department of Toshiba’s Semiconductor Company
  • “We’ve had consistent success in designing more compact, higher-performance ESD protection into our ICs with TakeCharge. We will continue to collaborate with Sarnoff to develop solutions for our future processes such as 45nm and 32nm.”   [read more]
• Shoji Ichino, general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited
  • “Fujitsu selected Sarnoff’s TakeCharge to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies. TakeCharge® will be Fujitsu’s primary ESD solution for their 65nm CMOS technologies after its full deployment in Fujitsu’s related standard IO libraries.”   [read more]

Relevant conference publications

Sarnoff engineers frequently publish technical peer-reviewed papers about the ESD solutions. A selection of these publications regarding advanced CMOS is provided below

• Outlook on ESD protection approaches for the emerging RF and high speed IC's in nanoscale technology nodes – Keynote Taiwan ESD symposium (2005)
• ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies – ISCAS (2005)
• Advanced ESD Protection Circuits in CMOS / SOI Nanotechnologies – CICC (2005)

Relevant brochures

Technical brochure for foundry CMOS 180nm - 130nm - 90nm - 65nm
TakeCharge Design Kit brochure for foundry CMOS 180nm - 130nm - 90nm - 65nm