Background

Consumers and companies expect an ever increasing bandwidth in the connection to the internet backbone as well as high data rates between home/office appliances and the main entry point in the home/office. The growing distribution of on-demand video or multi media content pushes the current infrastructure to the physical limits. Both well established multinationals as well as start-ups are creating new opportunities to increase the bandwidth of existing copper and fiber optic infrastructure. Such multi-gigabit networks require high performance switching and high speed data rates around and above 10Gbps, low power and low cost.

ESD complexity

The create economically viable circuits, IC designers rely on standard digital (foundry) CMOS nodes for the multimedia applications. However, mainstream CMOS process nodes (130nm – 90nm) include sensitive elements that are easily damaged during ESD stress. However, adding ESD protection onto the silicon die, adds parasitic capacitance to the IO pad which can possibly degrade the signal at higher frequencies. IO designers need low and stable (over signal voltage and frequency) capacitance and low resistance. Also the leakage of the ESD protection cell must be limited.

Experience from Sarnoff

Sarnoff has been working together with a number of customers (Fabless and IDM) in the field of communication applications. Currently the following IC applications are available on the market

Application	CMOS node
SerDes IO's in FPGA	180nm - 65nm
10Gbps Optical communications	180nm - 130nm

An example of application from one of our customers is the Electronic Dispersion Compensation for fiber optic transport. The flexible signal processing platform IC is released on 130nm TSMC and can work for data rates between 1Gbps and 10Gbps while consuming less than 600mW at the highest speed.

Key technical benefits for working with Sarnoff

IC designers have worked with Sarnoff to enable high speed throughput without compromising interface ESD performance.
For networking applications, Sarnoff has focused on different items:

• Area efficient ESD solutions to reduce the total ESD area as much as possible.
• Low capacitive, low resistive
  • High ESD protection with low cap: 100fF-200fF for 4kV
  • Low-to-zero resistance in the pad
• Scalable ESD performance to allow any ESD requirement on-chip.
• Low leakage and Latch-up immune devices
• Over voltage tolerant options available

Example circuit protection

An example of a protection concept for a SerDes application in 90nm is depicted below. The end user required 200V Machine Model (MM) on-chip ESD protection.

Low leakage during normal operation: 1nA @ 1.2V Low capacitive full local protection of sensitive analog IO: Total junction capacitance <190fF Small area for local protection: 1200 um2 Low noise, high speed enabled: No series resistance inserted between pad and input/analog IO

Customer testimonials

• Bradley Howe, vice president of IC Design at Altera,
  • “We chose TakeCharge® technology for our FPGA product families as part of Altera’s commitment to deliver high-performance, cost-effective programmable products to our customers. TakeCharge® has allowed us to effectively manage both ESD protection and IO area.”   [read more]
• Shoji Ichino, general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited
  • “Fujitsu selected Sarnoff’s TakeCharge to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies. TakeCharge® will be Fujitsu’s primary ESD solution for their 65nm CMOS technologies after its full deployment in Fujitsu’s related standard IO libraries.”   [read more]
• Renesas Technology
  • TakeCharge® ESD provides a high level of ESD protection in a smaller surface area, which allows the development of smaller chips. Finally, it has low parasitic capacitance, making it ideal for use in high-speed applications.   [read more]

Relevant conference publications

Sarnoff engineers frequently publish technical peer-reviewed papers about the ESD solutions. A selection of these publications regarding communication is provided below

• ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies - ISCAS (2005)
• Advanced ESD Protection Circuits in CMOS / SOI Nanotechnologies - CICC (2005)

Relevant brochures

Technical brochure for foundry CMOS 180nm - 130nm - 90nm - 65nm
TakeCharge Design Kit brochure for foundry CMOS 180nm - 130nm - 90nm - 65nm