Background

Recent applications require higher signal data throughput than ever before. PC (Serial ATA, PCI-express) and multimedia (DVI, HDMI) interfaces are running at speeds between 1Gbps and 10Gbps. At these data rates, the IO designer must carefully define the matching circuit connected at the bond pad. Impedance variations can cause reflections and ringing. Signal attenuation and degradation can cause the characteristic ‘eye’ measurement to close at the high frequencies. Many of these high speed interfaces rely on serial communication using differential LVDS or TMDS circuit concepts to channel the multimedia content between set top box, DVD player and TV receiver sets.

ESD complexity

The create economically viable circuits, IC designers rely on standard digital (foundry) CMOS nodes for the multimedia applications. However, mainstream CMOS process nodes (130nm – 90nm) include sensitive elements that are easily damaged during ESD stress. Certainly for the HDMI, DVI interfaces where the end user interaction can cause severe system level stress, robust and effective ESD protection must be in place. While many system makers relied on board-level ESD protection in the past, today most are working to include the ESD protection on-chip, requiring 8kV HBM (Human Body Model) protection.

However, adding ESD protection onto the silicon die, adds parasitic capacitance to the IO pad which can possibly degrade the signal at higher frequencies. IO designers need low and stable (over signal voltage and frequency) capacitance and low resistance. Also the leakage of the ESD protection cell must be limited because many of the Consumer Electronics appliances are powered from a battery.

Experience from Sarnoff

Sarnoff has been working together with a number of customers (Fabless and IDM) in the field of high speed IC applications. Currently the following IC applications are available on the market

Application	CMOS node
SerDes IO's in FPGA	180nm - 65nm
10 Gbps Optical communications	180nm - 130nm
HDMI	130nm
USB 2.0	130nm - 90nm
Serial ATA	130nm - 90nm

Key technical benefits for working with Sarnoff

IC designers have worked with Sarnoff to enable high speed throughput without compromising interface ESD performance.

For high speed interfaces, Sarnoff has focused on different items:

• Area efficient ESD solutions to reduce the total ESD area as much as possible.

• Low capacitive, low resistive

  • High ESD protection with low cap: 100fF-200fF for 4kV

  • Low-to-zero resistance in the pad

• Scalable ESD performance to allow any ESD requirement on-chip.

• Low leakage and Latch-up immune devices

• Over voltage tolerant options available

Example circuit protection

An example of a protection concept for a SerDes application in 90nm is depicted below. The end user required 200V Machine Model (MM) on-chip ESD protection.

Low leakage during normal operation: 1nA @ 1.2V Low capacitive full local protection of sensitive analog IO: Total junction capacitance <190fF Small area for local protection: 1200 um2 Low noise, high speed enabled: No series resistance inserted between pad and input/analog IO

Customer testimonials

• Bradley Howe, vice president of IC Design at Altera,

  • “We chose TakeCharge® technology for our FPGA product families as part of Altera’s commitment to deliver high-performance, cost-effective programmable products to our customers. TakeCharge® has allowed us to effectively manage both ESD protection and IO area.”   [read more]

• Shoji Ichino, general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited

  • “Fujitsu selected Sarnoff’s TakeCharge to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies. TakeCharge® will be Fujitsu’s primary ESD solution for their 65nm CMOS technologies after its full deployment in Fujitsu’s related standard IO libraries.”   [read more]

• Renesas Technology

  • TakeCharge® ESD provides a high level of ESD protection in a smaller surface area, which allows the development of smaller chips. Finally, it has low parasitic capacitance, making it ideal for use in high-speed applications.   [read more]

Relevant conference publications

Sarnoff engineers frequently publish technical peer-reviewed papers about the ESD solutions. A selection of these publications regarding high-speed interfaces is provided below

• ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies - ISCAS (2005)
• Advanced ESD Protection Circuits in CMOS / SOI Nanotechnologies - CICC (2005)

Relevant brochures

Technical brochure for foundry CMOS 180nm - 130nm - 90nm - 65nm
TakeCharge Design Kit brochure for foundry CMOS 180nm - 130nm - 90nm - 65nm